The escalating requirements for high density and performance associated with ultra-large scale integration semiconductor devices necessitate design rules of 0.18 micron and under, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features, e.g., of source, drain, and gate regions of transistors formed in or on a common semiconductor substrate, challenges the limitations of conventional contact and interconnection technology, including conventional photolithographic, etching, and deposition techniques.
Recently, there has been a demand for large-scale and ultra small-sized static random access memory (SRAM) devices in high performance complementary metal-oxide-semiconductor (CMOS) microprocessors. Manufacture of such devices require process compatibility with known salicide-CMOS technologies in order to avoid increasing the number of process steps. Conventional methods for reducing cell size include forming local interconnects to couple gates and doped regions. However, technologies utilizing an insulator-capped gate electrode are difficult to adapt for use with a salicide (self-aligned silicide) process, because they require the use of several additional photolithographic masks to etch off the insulator cap in the peripheral areas and to separately dope the gate and source/drain regions. While a damascene type local interconnect process affords some simplification of the fabrication scheme, such processing still requires additional chemical vapor deposition (CVD) of dielectric material, etching, chemical-mechanical planarization (CMP), photolithographic, and metallization steps. Another conventional technique for achieving smaller cell size involves shared-contact technology; however, such methods require contact implantation processing undesirably involving one or more masks in order to avoid junction leakage at the region of the contact on the LDD (lightly doped drain) regions.
Thus, there exists a need for a process for forming self-aligned silicide (i.e., salicide) contacts to transistor source and drain regions without reliance upon either a local interconnect or shared-contact. There exists a further need for methodology enabling the formation of contacts of proper size and alignment that reliably land on the desired areas of the semiconductor substrate and do not short to the gate. Moreover, there exists a need for a process for forming electrical contacts to transistor source and drain regions without shorting into the shallow trench isolation (STI) edge, and provide relatively low resistance local routing and ability to remote the contacts. There is also a need for a process which is compatible with conventional process flow for the manufacture of SRAMS and similar devices employing MOS transistors.